Digital systems do not emerge from C or Python. At the hardware level they are described in hardware description languages: languages that express parallelism, timing, and physical implementation in ways conventional programming cannot. VHDL is the most formally rigorous of those languages, and this module introduces it properly.
Students work with the industry-standard Xilinx and Mentor Graphics toolchains to take VHDL designs from specification through simulation and synthesis to implementation on a real FPGA development board. The path from description to silicon is one that many engineers know in theory but fewer have walked in practice.
As a PGTA on this module, I supported laboratory sessions and student work through the design and simulation exercises.
Why it matters
FPGAs and custom digital logic are increasingly important in high-performance computing, embedded systems, signal processing, and AI acceleration hardware. The ability to design at the RTL level, verify designs through simulation before synthesis, and understand what the synthesiser actually does with VHDL code, gives students a capability that is rare even among hardware engineers.
The formal structure of VHDL, with its strict type system, concurrency model, and explicit distinction between simulatable and synthesisable code, also develops a precision in technical thinking that transfers to other engineering contexts. A student who understands why some VHDL constructs cannot be synthesised understands something deep about the relationship between description and implementation.
Learning outcomes
By the end of the module, students can:
- Apply FPGA design flow in a commercial design package
- Use VHDL simulation in a commercial simulator
- Write synthesisable VHDL to design basic combinational and sequential circuits
- Design testbench code to verify VHDL designs through simulation
- Synthesise and implement VHDL designs on a commercial development board
Assessment
- 30% Coursework: VHDL design project
- 30% Laboratory submissions (six labs, 5% each)
- 40% End-of-module examination (2 hours)
What students leave with
Students can describe, simulate, synthesise, and implement digital circuits in VHDL using professional-grade toolchains. They have completed the full FPGA design flow from specification to physical implementation, which is exactly the experience that roles in FPGA engineering, digital design, and hardware-software co-design require.